1. Field of the Invention
The present invention generally relates to semiconductor devices, and particularly to reduction of current consumption in standby state of a semiconductor device having therein a dynamic semiconductor memory device requiring refresh.
2. Description of the Background Art
Recently, as personal digital assistants have widely been used, a semiconductor memory device is required to have smaller size and lower power consumption. The semiconductor memory device is often employed being integrated on one chip with a microcomputer and a large-sized logic circuit. An integrated circuit on which various circuits of such large size are mounted to implement system-on-chip is herein referred to as system LSI.
A conventional structure of a semiconductor memory device is first described before discussion on reduction in supply current consumption of the system LSI.
FIG. 35 is a schematic block diagram showing a structure of a conventional semiconductor memory device 1000.
Referring to FIG. 35, semiconductor memory device 1000 includes an external clock signal input terminal 1116 receiving externally supplied complementary clock signals ext.CLK and ext./CLK, clock input buffers 1084 and 1085 buffering the clock signals supplied to external clock signal input terminal 1116, an internal control clock signal generating circuit 1118 receiving respective outputs of clock input buffers 1084 and 1085 to generate internal clock signal int.CLK, and a mode decoder 1120 receiving an external control signal supplied to an external control signal input terminal 1110 via input buffers 1012-1020 which operate according to internal clock signal int.CLK.
External control signal input terminal 1110 receives clock enable signal CKE, chip select signal /CS, row address strobe signal /RAS, column address strobe signal /CAS and write control signal /WE.
Clock enable signal CKE is used to allow a control signal to be input to the chip. If this signal is not activated, input of the control signal is not permitted and semiconductor memory device 1000 does not accept signal input from the outside.
Chip select signal /CS is used for determining whether a command signal is input or not. When this signal is activated (at L level), a command is identified according to a combination of levels of other control signals at the rising edge of the clock signal.
Mode decoder 1120 outputs an internal control signal for controlling an operation of an internal circuit of semiconductor memory device 1000 according to these external control signals. Mode decoder 1120 outputs, as internal control signals, signal ROWA, signal COLA, signal ACT, signal PC, signal READ, signal WRITE, signal APC and signal SR.
Signal ROWA indicates that row-related access is made, signal COLA indicates that column-related access is made, and signal ACT is used to instruct that a word line is activated.
Signal PC specifies precharge operation to end a row-related circuit operation. Signal READ instructs a column-related circuit to perform reading operation, and signal WRITE instructs the column-related circuit to perform writing operation.
Signal APC specifies auto precharge operation. When the auto precharging operation is designated, precharge operation is automatically started simultaneously with the end of a burst cycle. Signal SR designates self refresh operation. When the self refresh operation starts, a self refresh timer operates. After a certain time passes, a word line is activated and the refresh operation starts.
Semiconductor memory device 1000 further includes a self refresh timer 1054 which starts its operation when self refresh mode is designated by signal SR and then designates activation of a word line, i.e., start of the refresh operation when a certain time passes, and a refresh address counter 1056 for generating a refresh address according to an instruction from self refresh timer 1054.
Semiconductor memory device 1000 further includes a reference potential input terminal 1022 receiving signal VREF which is to be used as a reference for determining whether an input signal is H or L level, a mode register 1046 holding an address signal supplied via an address signal input terminal 1112 as well as information regarding a predetermined operation mode, for example, information regarding burst length according to a combination of external control signals described above, a row address latch 1250 receiving address signals via address input buffers 1032-1038 operating according to internal clock signal int.CLK2 to hold, when a row address is input, the input row address, a column address latch 1550 receiving address signals A0-A12 to hold, when a column address is input, this column address, a multiplexer 1058 receiving respective outputs from refresh address counter 1056 and row address latch 1250 to select the output from row address latch 1250 in the normal operation and select the output from refresh address counter 1056 in self refresh operation and accordingly output the selected one, and a row predecoder 1136 receiving an output from multiplexer 1058 to predecode a row address.
Semiconductor memory device 1000 further includes a burst address counter 1060 generating an internal column address according to burst length data from mode register 1046 based on the column address held in column address latch 1550, a column predecoder 1134 receiving an output of burst address counter 1060 to predecode a corresponding column address, a bank address latch 1052 receiving bank addresses BA0-BA2 supplied to an address input terminal via input buffers 1040-1044 which operate according to internal clock signal int.CLK, and a bank decoder 1122 receiving an output of bank address latch 1052 to decode a bank address.
The address signal supplied to address signal input terminal 1112 is also used for writing data in the mode register by a combination of any bits when operation mode information is written into the mode register. For example, burst length BL, value of CAS latency CL and the like are designated by a combination of a predetermined number of bits of an address signal.
Bank address signals BA0-BA2 designate an access bank in each of the row-related access and the column-related access. Specifically, in the row-related access and the column-related access each, bank address signals BA0-BA2 supplied to address signal input buffers 1040-1044 are taken by bank address latch 1052 and then decoded by bank decoder 1122 to be transmitted to each memory array block (bank).
In addition, semiconductor memory device 1000 includes memory array blocks 100a-100g respectively serving as banks 0-7 each for independent reading/writing operation, a row decoder 1244 for selecting a row (word line) in a corresponding bank according to respective outputs from bank decoder 1122 and row predecoder 1136, a column decoder 1242 for selecting a column (bit line pair) in a corresponding bank according to an output from column predecoder 1134, an I/O port 1266 supplying data read from a selected memory cell in a selected bank to a global I/O bus G-I/O in reading operation and supplying write data transmitted by bus G-I/O to a corresponding bank in writing operation, a data input/output circuit 1086 holding externally supplied write data and supplying it to bus G-I/O in writing operation and holding read data transmitted by bus G-I/O in reading operation, and bidirectional input/output buffers 1072-1082 for transmitting input/output data DQ0-DQ31 between data input/output circuit 1086 and data input/output terminal 1070.
Bidirectional input/output buffers 1072-1082 operate in synchronization with the internal clock signal according to operation mode data held in mode register 1046.
FIG. 36 illustrates power supply potential applied from the outside to a conventional system LSI.
Referring to FIG. 36, the system LSI includes a chip CH on which a logic portion LG and a DRAM portion MEM are mounted. The DRAM portion includes a power supply generating circuit VGEN1 generating boosted potential VPP and a power supply generating circuit VGEN2 generating substrate potential VBB.
The logic portion LG receives supply potential LVDDH of 3.3V applied from the outside via a terminal T50 and potential LVDDL of 1.5V applied via a terminal T51. The DRAM portion MEM receives supply potential DVDDH of 3.3V applied from the outside via a terminal T52 and supply potential DVDDL of 1.5V applied via a terminal T53.
In such a system LSI, in order to cut supply current consumption in the standby state while data stored in a memory cell of the DRAM portion MEM is maintained, supply potentials LVDDH and LVDDL applied to the logic portion LG are set at 0V to stop power supply current from being applied. In this way, current consumption in the logic portion LG in the standby state is reduced.
Preferably personal digital assistants and the like can be operated by a battery as long as possible. In order to achieve this, power consumption of the system LSI should be reduced as much as possible.
The DRAM portion included in the system LSI requires refresh operation even in the standby state in order to preserve data stored in a memory cell. The refresh operation is carried out in every one cycle at regular intervals, or all of memory cells are successively refreshed and this successive refresh is carried out at regular intervals. In any case, during the period in which the refresh operation is performed, any circuit operation is carried out in the DRAM portion, which accompanies leakage current upon activation of a transistor. The leakage current in operation and in standby state increases as threshold voltage of an employed MOS transistor is decreased in order to accelerate the speed of operation and to lower the power supply potential. As a result, current consumption of the entire device increases.
FIG. 37 illustrates power supply potential applied to peripheral circuitry of the DRAM portion MEM shown in FIG. 36.
Referring to FIGS. 36 and 37, power supply potential DVDDL applied to the DRAM portion MEM is provided to a clock control unit 1402, a row-related command control unit 1404, a column-related command control unit 1406, a row-related address control unit 1408, a bank address control unit 1410, a column-related address control unit 1412, an input/output data-related control unit 1414 and a self refresh-related control unit 1416. Supply potential DVDDL is also applied from the outside to the peripheral circuitry except for the memory array portion shown in FIG. 36 in the conventional device. For this reason, a considerable leakage current is generated in the standby state in any circuit which is unnecessary in the refresh operation, for example, input/output data-related control unit 1414 and the like.
One object of the present invention is to provide a semiconductor device having a power down mode which enables power supply current to be consumed less while information stored in a DRAM portion is preserved in standby state.
The present invention, in brief, is a semiconductor device transmitting/receiving data in a normal mode and performing refresh of stored data with reduced current consumption in the power down mode. The semiconductor device includes a memory array, a first peripheral circuit and a second peripheral circuit.
The memory array includes a plurality of memory cells arranged in a matrix of rows and columns. The first peripheral circuit inputs/outputs data to be stored in a memory cell in the normal mode. The first peripheral circuit stops its operation for reducing current consumption in the power down mode. The second peripheral circuit controls refreshing of data held in a memory cell in the power down mode.
Accordingly, a major advantage of the present invention is that reduction of current consumption is possible by stopping the first peripheral circuit from operating in the power down mode.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.